The present invention relates to a phase adjustable delay circuit and to a technique for phase adjusting a clock signal that is connected to different components on circuit board to synchronize the arrival of the clock signal at various points on the circuit board.
Clock chips typically generate a particular clock signal (or several synchronized clock signals at frequency multiples) for distribution to multiple points on a circuit board. At the clock rates of current clock chips, synchronizing the arrival time along the various paths to the different points on the circuit board is a difficult task. The current solution is to use “serpentine traces” in which otherwise-too-short paths are lengthened by having the traces zigzag across the circuit board while traces to distant points on the circuit board are more direct. This inefficiently uses circuit board area, radiates additional electromagnetic interference (EMI) for the lengthened paths, and cannot be easily altered during circuit board debugging after circuit board assembly.
Consequently, a delay circuit and method is needed to simplify the synchronization of a clock signal distributed to different points on a circuit board.